1. Field of the Invention
The present invention generally relates to the integration of guard rings in a computer-aided design, verification, and checking system, and more particularly, for design integration of guard rings into computer chips.
2. Description of the Related Art
Guard rings are important in designs to isolate single components, circuits, sub-circuits, and functional design blocks. In single components, guard rings are used to prevent parasitic interaction between circuits, minimize carrier injection, latchup, and circuit coupling. Guard rings are used between NFETs, and PFETs to minimize CMOS latchup. Guard rings are used in ESD networks to isolate ESD networks from I/O circuits. Guard rings are used between I/O and core circuitry to isolate peripheral circuits from the core circuit.
As electronic components become smaller and smaller (along with the internal structures in integrated circuits) it is easier to either completely destroy or otherwise impair electronic components with latchup. Latchup occurs when a pnpn structure transitions from a low current high voltage state to a high current low voltage state through a negative resistance region (i.e. forming an S-Type I-V (current/voltage) characteristic).
Latchup is typically understood as occurring within a pnpn structure, or silicon controlled rectifier (SCR) structure. Interestingly enough, these pnpn structures can be intentionally designed, or even unintentionally formed between structures. Hence, latchup conditions can occur within peripheral circuits or internal circuits, within one circuit (intra-circuit) or between multiple circuits (inter-circuit).
Latchup is typically initiated by an equivalent circuit of a cross-coupled pnp and npn transistor. With the base and collector regions being cross-coupled, current flows from one device leading to the initiation of the second (“regenerative feedback”). These pnp and npn elements can be any diffusions or implanted regions of other circuit elements (e.g., P-channel MOSFETs, N-Channel MOSFETs, resistors, etc) or actual pnp and npn bipolar transistors. In CMOS, the pnpn structure can be formed with a p-diffusion in a n-well, and a n-diffusion in a p-substrate (parasitic pnpn). In this case, the well and substrate regions are inherently involved in the latchup current exchange between regions.
The condition for triggering a latchup is a function of the current gain of the pnp and npn transistors, and the resistance between the emitter and the base regions. This inherently involves the well and substrate regions. The likelihood or sensitivity of a particular pnpn structure to latchup is a function of spacings (e.g. base width of the npn and base width of the pnp), current gain of the transistors, substrate resistance and spacings, the well resistance and spacings, and isolation regions.
Latchup can be initiated from internal or external stimulus. Latchup is known to occur from single event upsets (SEU). Single event upsets can include terrestial emissions from nuclear processes, and cosmic ray events, as well as events in space environments. Cosmic ray particles can include proton, and neutron, gamma events, as well as a number of particles that enter the earth atmosphere. Terrestial emissions from radioactive events, such as alpha particles, and other radioactive decay emissions can also lead to latchup in semiconductors.
Latchup can occur from voltage or current pulses that occur on the power supply lines, such as VDD and VSS. Transient pulses on power rails (e.g. substrate or wells) can trigger latchup processes. Latchup can be initiated by negative transient on the VDD which can lead to a forward biasing of all the n-diffusions and n-well structures and electron injection through out the semiconductor chip substrate. This produces a “sea of electrons” injected in the chip substrate. Equivalently, a positive transient on the VSS can lead to hole injection, and forward biasing of the substrate-well junction providing a “sea of holes” event. Latchup can also occur from a stimulus to the well or substrate external to the region of the thyristor structure from minority carriers.
In internal circuits and peripheral circuitry, latchup is a concern can also occur as the result of interaction of the ESD device, the I/O chip driver, and adjacent circuitry initiated in the substrate from overshoot and undershoot phenomenon. These can be generated by CMOS off-chip driver circuitry, receiver networks, and ESD devices. In CMOS I/O circuitry, undershoot and overshoot can lead to injection in the substrate. Hence, both a p-channel MOSFET and n-channel MOSFET can lead to substrate injection. Simultaneous switching of circuitry where overshoot or undershoot injection occurs, leads to injection into the substrate which leads to both noise injection and latchup conditions. Supporting elements in these circuits, such as pass transistors, resistor elements, test functions, over-voltage dielectric limiting circuitry, bleed resistors, keeper networks, and other elements can be present leading to injection into the substrate. ESD elements connected to the input pad can also lead to latchup. ESD elements that can lead to noise injection, and latchup include MOSFETs, pnpn SCR ESD structures, p+/n-well diodes, n-well-to-substrate diodes, n+diffusion diodes, and other ESD circuits. ESD circuits can contribute to noise injection into the substrate and latchup.
In a semiconductor chip environment, there exists a plurality of different stimulus as well a plurality of circuit functions. Peripheral circuits include ESD networks, transmitter and receiver networks, system clocks, phase lock loops, capacitors, decoupling capacitors and fill shapes. Internal circuits can consist of DRAM memory, SRAM memory, gate arrays, and logic circuitry. Latchup can occur between interactions within a given circuit, or between circuits. In this complex environment, the latchup event can be an interaction of inter-circuit interaction or intra-circuit interactions.
Additionally, the interaction of the different circuits can lead to an initiation of a primary latchup event followed by a secondary latchup event. Since the circuits in a complex chip are coupled through the substrate, well, and power rails, circuit blocks and elements within a circuit block can be interactive.
By using guard ring structures, the likelihood of latchup in an integrated chip is decreased. The efficiency of the guard ring to prevent latchup is a function of the physical dimensions (height, width and depth), type, placement, and electrical connections. Verification and checking of guard rings has been difficult since guard rings do not have distinguishing features significantly different from standard shapes. As a result, in a GYM environment, and GL1, traditionally there was no means to verify the existence of guard rings as a design guideline or requirement in circuits and chips.
In an ESD design checking system, guard rings were “checked” by placement of the I/O dummy and ESD dummy virtual levels on the guard ring structure. This unfortunately caused two problems. One, the placement was not done systematically causing problems with fill shapes, fill excludes, and other spacing issues. Second, the placement was not identical in each design. Third, there was no means to verify the placement of the ESD and whether the I/O dummy was in fact on the guard ring structure. Hence, the placement and inclusion of the guard ring had no true verification and checking means.
Guard rings were never integrated in a fashion that addressed the true value of the design. Many designers did not place contacts, wiring, bussing, and physical dimensions leading to poor design practices and inadequate guard rings. The guard ring efficiency for all guard rings in designs were different and never consistent. Today, there is no means of evaluation of the guard ring efficiency from circuit design to model or means to determine latchup failure. In the design system, there was no symbology to verify the existence of guard rings in the schematics for visual verification. There was no means of checking, verification using LVS, DRC or other means.
In a Cadence based design systems (available from IBM Corporation, Armonk, N.Y., USA), there are presently no means of verification, checking and placement of guard ring structures. In a Cadence based system, a new design system was developed for ESD networks in mixed signal and RF applications. The ESD designs are hierarchical which are allowed to grow in physical dimension based on the user's choice of inherited parameters. In this system, these designs can be placed into existing space with existing guard rings from adjacent structures. Symbols exist for these designs but without a means to verify the existence or non-existence of guard rings.
It is the motivation of the inventors to provide checking and verification of a guard ring structure presence on a circuit where required. It is also the motivation of the inventors to integrate the guard ring efficiency into the design system and provide a design which has visual symbology which integrates with existing symbology of circuit elements, sub-circuit blocks, and circuit blocks. It is additionally the motivation of the inventors to allow for a grow-able guard ring which expands with a circuit, circuit block, and circuit function.